Principal Memory Architect (729307)

Contract, Open
Santa Clara CA
Posted 7 months ago

Job description:

  • Attend JEDEC committee meetings and weekly Task Groups, providing timely and relevant information to keep R&D team up-to-date on industry progress, and bring the new development and specification to the team. Prepare and deliver company’s point of view and position to the committee, and compare with other company’s solution and positions, vote on motions. Explain the “how and why” of proposed ballots.  Covering DDR5, LP-DDR5 and NV-DIMM-P. 
  • Analyze and evaluate memory subsystems, including memory controllers, memory signal routing and power delivery on evaluation boards, DRAM components, support logic components and DIMM modules.  Evaluation test chips and product, both pre- and post-power-on. Analysis of functionality, memory sub-system performance and system energy efficiency. Covering DDR5, LP-DDR5 and NV-DIMM-P technologies.
  • To support analysis and evaluation of memory systems, make quarterly face-to-face trips, providing on-site consulting at HQ in Shenzhen.  Meet with architects and designers to deliver technical presentations, and hold in-depth discussions.  Provide team with training on DRAM, DIMM and Memory Controller specifications and guidelines.
  • Consolidate all DDR5 JEDEC work-in-progress, consensus, ballots and status into one working document.  Include “how and why” of new DDR5 features, and guidelines for implementation.  Covers material relevant to HiSilicon development, including DDR5 component specs, R-DIMM, LR-DIMM and NV-DIMM interface specs, and RCD and DB interface specs. 
  • To support analysis and evaluation memory systems, send all final JEDEC ballots to team ahead of each JEDEC JC-16/40/42/45/63/64 committee meeting, along with a spreadsheet organizing the voting effort. Summarize and make voting recommendations on DDR5 and NV-DIMM ballots.

Job Requirements:

  • Solid knowledge with DRAM technology and memory controller architecture, algorithm, processor and validation; system architecture, power management, reliability, thermals, signal integrity, ASIC and board design.
  • Good hands-on experience on representing large organizations in international standard bodies and driving broad industry standards.
  • Proven track record of leading complex projects for premier industry research lab.
  • Advanced degree with MS+ in electrical engineering and related area.
  • Good communication skills, and willing to travel around in the US and to China.

Job Features

DurationUntil 11-Sep-2020

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